On Fault Tolerant Multistage Interconnection Networks

Abstract

The performance of a computer system depends directly on the time required to perform a basic operation and the number of these basic operations that can be performed concurrently. High performance computing systems can be designed using parallel processing. Parallel processing is achieved by using more than one processors or computers together they communicate with each other to solve a given problem. An interconnection network is a complex connection of switches and links permitting processors in a multiprocessor system to communicate among themselves or with memory modules. Multistage interconnection networks play an important role in parallel systems. Multistage Interconnection Networks (MINs) consist of more than one stages of small interconnection elements called switching elements and links interconnecting them. MINs provide better way for the communication between different processors or memory modules with less complexity, fast communication, good fault tolerance, high reliability and low cost. In this thesis two new networks MASEN and IASEN are proposed. These two networks are derived from an existing regular network ASEN-2. Both MASEN and IASEN are irregular networks, they have different number of switches at each stage. ASEN-2 network is a single switch fault-tolerant. If both switches in a loop are simultaneously faulty then some sources are disconnected from some destinations. MASEN and IASEN provides multiple paths between each source and destination pair. It has been found that the bandwidth of both MASEN and IASEN is almost double than the existing ASEN-2 network. Reliability of MASEN and IASEN network is better than ASEN-2 and these networks also provides better permutation capabilities. For the small size networks cost of MASEN is less than ASEN-2 but it increases as the network size increases. whereas the cost of IASEN is little bit higher than ASEN-2.