UVM Environment Bring-Up for AXI4 Full Based DMA IP

Abstract

This project report details the comprehensive verification process for the AXIMM Interface of a DMA IP, focusing on ensuring its functionality, correctness, and adherence to specifications. Direct Memory Access (DMA) is crucial in modern computer architecture, particularly when transferring data between a host machine and an FPGA accelerator. A modular DMA core on the FPGA alleviates the host CPU during transfers, conserves resources, and improves performance. It is essential to verify the functionality of a DMA IP before implementing it on an FPGA. The verification methodology employed includes simulation, formal verification, and emulation techniques to thoroughly validate the IP's design. Key areas covered are functional correctness, protocol compliance, performance analysis, and coverage metrics. The report discusses the challenges faced during verification and the strategies used to overcome them, ultimately ensuring the AXIMM's reliability and robustness for integration into the DMA IP. The team designed reusable sequences, scoreboards, and tests, with the overall testbench structure based on a basetype test. Different tests extend this base-type test and use type overriding with the UVM configuration database to employ various scoreboards and sequences as needed.