Optimization of test scheduling of SOC using Genetic Algorithm

Abstract

Integration of a complex system, that until recently consisted of multiple Integrated Circuits, onto a single Integrated Circuits, is known as System On a Chip. The shrinking of silicon technology leads to increase in number of faults which in turn leads to the serious increase in test time. Test time reduction is one of the research challenge in the SOC design. The test-application time when testing a system can be minimized by scheduling the execution of the test sets as concurrently as possible. The basic idea in test scheduling is to minimize the test application time. Many system-on-chip (SOC) integrated circuits today contain hierarchical cores that have multiple levels of design hierarchy involving “child cores”. Hierarchy imposes a number of constraints on the manner in which tests must be applied to parent cores and their child cores. In this thesis we explore and analyze all the previous work on TAM optimization and test scheduling for testing of SOCs taking into consideration test access time. It has been found that all the previous work done in TAM co-optimization and test scheduling for testing has treated all the cores in the SOC as if at same level of hierarchy i.e. flat cores. We perform optimization of TAM width sharing. We explore the impact of different TAM width on test application time.