Design and Analysis of Low Power SRAM

Abstract

Power has been a major issue in SoC designs with the contemporary sub-micron technologies. . It has thus become very important to control the power and address the power dissipation throughout the design cycle right from the architectural level. For 180nm and below technologies, leakage is the main factor which dominates over the dynamic power and contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. According to some authenticated reports, 40% or more of the total power consumption is due to the leakage of transistors. This percentage is likely to increase with technology scaling unless effective techniques are introduced to bring leakage under control. This report presents several topology based leakage reduction mechanism applicable to a standard 6-T SRAM cell. Substantial reduction in the leakage current in standby mode has been obtained. The leakage current components considered in present work are gate leakage and subthreshold leakage. This thesis has been organized into 6 sections. The first chapter presents an introductory overview of semiconductor memories in general and SRAM in particular with a compressive review of contemporary literature. The second chapter reviews the leakage current components inside an SRAM cell and popular techniques to tackle the issue. Third and Fourth chapter summarizes the proposed topologies when yield substantial reduction in off state leakage. Finally chapter five and six describe simulation based performance comparison and conclusion derived from this work respectively.