Comparison of 8-bit Multipliers Designed in Different Non-Clocked Logic Styles on the Basis of Power

Abstract

This thesis work focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. Furthermore, the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation, alternative solutions at each level of abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this thesis work different non-clocked logic styles have been compared on the basis of power. The advantage of non-clocked logic styles is that there is less switching power in these styles because there no clock is used. Among DCVS, DSL and CNTL logic styles, CNTL consumes less power because there is less dynamic power dissipation in CNTL. Multiplier is the most commonly used circuit in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. There are various types of multipliers available depending upon the application in which they are used. Full Adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. 8-bit CNTL multiplier consumes least power among the three non-clocked logic styles which has been discussed in the thesis.