Verification of APB Protocol and Integrating Tool for Repeaters

Abstract

Grasping the AMBA Advanced Peripheral Bus (APB) protocols is essential for interfacing with low-bandwidth peripherals such as keyboards, UARTs, and timers, which do not demand the high-frequency operations necessary for memory access or processor requests. The early verification of APB protocol can be achieved by developing the APB Protocol with HDL (System Verilog) and conducting verification through Universal Verification Methodologies (UVM) requires a solid comprehension of UVM's built-in classes, functions, and methods. This knowledge facilitates the construction of an effective Test Bench structure. Additionally, being a member of the Graphics Processing Units (GPUs) team that focuses on tools and methodologies, I recognize the critical role that Repeaters play in minimizing signal delay from the sender to the target. Many microprocessors developed at Intel necessitate the use of signal repeaters at the Full chip level to a certain extent. The implementation of Repeaters is essential for enhancing the speed of a net and for improving signal slope. It is crucial to comprehend the Repeater insertion process thoroughly. Repeaters Insertion is a tedious task by keeping in mind all the constraints like timing closure and minimization of the power but one of the problems we need to avoid is the formation of loops this caused. Once we are done with inserting repeater in one partition, we cannot come back for the same partition for repeater Insertion. The loops can be avoided by tracing those nodes where loops can be formed, after tracing the nodes we can insert the repeaters by skipping those nodes keeping track of constraints.