Modeling and Performance Analysis of Double Gate Carbon Nanotube Field Effect Transistor

Abstract

Since several years ago, it has been understood that silicon transistors are difficult to further shrink after a particular feature size. In next decade or two, ability to advance MOSFET technology will start to decline, necessitating a rush to find a replacement. The present research investigates the possibility of replacing traditional MOSFETs due to a variety of short-channel effects, including threshold voltage variations, leakage current, and drain-induced barrier lowering at the nanoscale. Researchers are looking at using carbon nanotubes—rolled-up graphene sheets—instead of silicon in electronic devices. Replacement of MOSFETs with this new kind of transistors, referred to as carbon nanotube field effect transistors (CNTFETs), is currently a leading technology at nanoscale. With their excellent thermal conductivities, high current drivability and superior transport characteristics, use of CNTs have emerged as a potential replacement for bulk CMOS technology. Despite all development and advancement, various challenging issues still need to be resolved. Therefore, in order to proceed in research, this thesis reviews all previously done research and explains the research that will be needed in future to produce large-scale VLSI chips using CNTFETs. Models for design and study of CNTFETs are presented in this thesis. Applications for these transistors in emerging field of nanotechnology are being given important consideration. In this work, double gate carbon nanotube field effect transistor (DG-CNTFET) are considered to overcome various short channel effects. An analytical model that is temperature dependent has been proposed for drain current of DG-CNTFET to analyse device performance at variable temperature range. This developed model is used to obtain current-voltage characteristics of DG-CNTFET in MATLAB to compare results obtained in nano TCAD ViDES. For varying temperature ranges, several performance parameters including output characteristics, ON and OFF currents, subthreshold swing and drain conductance have also been obtained to analyze the effect of thermal environmental conditions on device performance. Subthreshold swing increases with rise in temperature and drain conductance increased by 4 times when there is increase in temperature from 250 K to 400 K. Further, temperature dependent performance analysis of threshold voltage and channel parameters’ effect on threshold voltage of DG-CNTFET are presented. To evaluate device performance under thermal environmental conditions, temperature effects have been taken into account. Also, evaluation of DG-CNTFET and DG-MOSFET’s threshold voltages at varying temperatures has been performed. It was found that the DG-CNTFET has small variation in vi threshold voltage at different temperatures, which makes it more appropriate to use in applications where thermal environmental conditions must be taken into account for design purposes. This is because of unique property of thermal stability found in CNTs in comparison to DG-MOSFET. These results can be effectively applied to these devices' design considerations. CNTFETs have become prominent in arena of applications. One of the major applications in which CNTFET can be applied is SRAM cell. SRAM is a kind of memory that is frequently utilized in low power consuming gadgets. In fact, SRAM cells use the majority of transistors present in many integrated circuits, accounting for 85%–90% of integrated circuits on die used for this type of memory. Scaling down SRAM has become necessary due to increased requirement for low power, high speed devices like smartphones and tablets as well as introduction of IoT devices. Since standard CMOS devices are used to make SRAM, all issues with MOSFET scaling also exist for SRAM scaling. This research focuses on analysis of 6T CNTFET SRAM cell, including its benefits and drawbacks when compared to CMOS based 6T SRAM cell, as well as several performance parameters including propagation delay, power dissipation and power delay product (PDP). Furthermore, CNTFET technology has been used to analyze SRAM cell and it is then a comparison is made with CMOS 6T SRAM cell. The goal is to find trends for various parameters at various technology nodes. Various findings have been obtained after the models are simulated. The results showed that 6T SRAM cell based on CNTFET outperforms CMOS based 6T SRAM cell due to its lesser power dissipation and propagation delay which can further be used for low power and high speed applications. It was concluded that CNTFETs are better contenders to replace traditional MOSFETs at the nanoscale in the VLSI industry as they reduce several short-channel effects.