Real Time Implementation of Sobel Edge Detector on FPGA

dc.contributor.authorSinghal, Dhruv
dc.contributor.supervisorKumar, Vinay
dc.date.accessioned2016-08-02T11:29:41Z
dc.date.available2016-08-02T11:29:41Z
dc.date.issued2016-08-02
dc.description.abstractImage processing is a computationally intensive operation and typically done in software using CPU processing power. However, even with the advances in computing technology today, software-based image processing requires expensive and powerful CPUs to perform real-time image processing. This is where a low cost FPGA based image processing solution becomes useful. It eliminates the need for powerful CPUs and at the same time can perform real-time processing relatively easily. This work presents the implementation of such an image processing solution in hardware, using a FPGA at its core. The high level goal is to detect edges of an image and the algorithm used for this purpose is Sobel edge detection. Edge detection is the fundamental operation in image analysis. It has to be done for any high end application, such as security cameras. There are various image detection techniques available. These include- Canny, Krisch, Lapla1 and Lapla2. As compared to other techniques Sobel has been chosen for the research work, over the other techniques, because of its simplicity and moderate average risk (AVR) to signal to noise (SNR) ratio.en_US
dc.identifier.urihttp://hdl.handle.net/10266/3984
dc.language.isoenen_US
dc.subjectFPGA, HDL, Sobel, Verilog, VGAen_US
dc.titleReal Time Implementation of Sobel Edge Detector on FPGAen_US
dc.typeThesisen_US

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