Design of 10 Bit Sample and Hold Amplifier.

Abstract

The highest bandwidth signal that can be digitized by an analog-to-digital converter is often govern by the performance of a preceding sample-and-hold circuit. Open-loop sample and hold topologies generally provide the fastest implementation of the sampling function. However, the precision obtained with such configurations is typically much lower than can be achieved with alternative closed-loop architecture. In design where an MOS transistor is used as sampling switch, input-dependent charge associated with the fast turn-off of the switch is often the principal source of sampling error. This charge injection introduces a pedestal error S V , in the hold mode that results in both nonlinearity and gain error. Moreover, the pedestal error is not well-controlled and is therefore difficult to compensate for using self-calibration techniques. In this thesis, the fully differential sample and hold circuit has been designed and simulated on 1.25um CMOS technology in order to meet the given specifications. This design is free from the non-linearities such input-dependent charge etc as stated above that are present in open-loop or single ended configuration. The circuit designed is capable of sampling the input in the range of 2-8MHz with the precision of 10-bits, having clock frequency of 20MHz.