FPGA based Implementation of Test and Debug Environment for High Speed Serial Links

Abstract

Testing and debugging are two emerging domains in the era of VLSI design. The accelerating upward trend in operating frequencies for chips used in almost all the application domains has tremendous implications for both chip design and manufacturing. The performance problems may also arise from the increasing scale of tasks performed on the chip, process complexity, more complex fabrication steps, various dielectrics and multiple threshold devices. So it becomes quit important to test and debug a chip. At-speed testing is very much crucial for reducing test time. This report presents the “FPGA based Implementation of test and debug environment” for at speed functional testing and validation of ULPI PHY. The fundamental purpose of this “test and debug” platform is to verify procurement ULPI specifications, what was specified is what was delivered: it verifies that the device meets the functional, performance, design, and implementation requirements identified in the procurement specifications. This FPGA based test and debug platform also ensures the bit error rate (BER) for end to end performance and quantifies the reliability of the entire system from “bits in” to “bits out”. Jitter is a dominant factor in affecting the BER of a USB data communication system. It may alter the sampling of the data and cause timing mismatch. So BER must be calculated under the worst case incorporating both transmitter and receiver clock jitter into the USB communication system.