Electrical Tuning of Optical Delay in Graphene based Photonic Crystal Waveguide

Abstract

Optical signal processing is an efficient and powerful enabler for various communication functions. One of the basic building blocks for achieving efficient and reconfigurable signal processing is a continuously tunable optical delay line. Tunable optical delay lines have various applications in high-performance optical switching and signal processing. The ability to control the group velocity and group delay of slow light can find applications to realize devices for variable delay lines and optical storage and buffering. The purpose of our research is to design and analyze a graphene based photonic crystal waveguide for delay tuning applications. In this dissertation, an electrically controlled graphene based line-defect photonic crystal waveguide is proposed for tuning the group delay. Graphene, a twodimensional monolayer of carbon atoms, is attracting significant interest due to its unique optical, electrical and chemical properties and its ability to be integrated with existing wave guiding materials such as silicon. It is found that the introduction of few-layer-graphene into photonic crystal waveguide can slow down the guided light. Two designs are proposed: one with graphene on the core region (line-defect) and other with graphene on the cladding region. At telecommunication wavelength 1550 nm, the group delay is tuned from 43 picoseconds to 72 picoseconds in the first design and from 58 picoseconds to 87 picoseconds in the second device design on varying the applied voltage (on graphene) from 1 volt to 4 volts. A group delay tuning of 29 picoseconds is reported with both the designs. Presence of graphene not only provides the way to electrically tune the delay (with low-power) but it also enhances the group delay to some extent. This delay reconfigurability will open up a whole new field of nonlinear signal processing using slow light. The proposed photonic crystal waveguide with graphene can be promising for realization of low-power electrically controllable on-chip delay lines.