VLSI Architectures of Turbo Decoder

Abstract

Turbo codes are one of the most successful error correction codes. Due to the use of Pseudo random interleaves, encoded data appears to be random in channel, yet turbo decoders are intelligent enough to decode the original data. And also due to its inherited recursive nature to use soft inputs and outputs, it provides better BER compared to convolution codes. But there is a price to pay for better communication performance is in terms of Storage requirement, decoding delay and computation complexity. The objective of this thesis work is to analyse different Soft Input Soft Output (SISO) a posterior probability (APP) turbo decoders at architecture level which gives different performance metrics in terms hardware requirement and throughput. I used a graphical approach known as Tile-graph to analyse different implementations of SISO APP Turbo decoder, which provides an estimate of decoding delay and hardware requirement. Two different optimized approaches, Sliding Window and Parallel Window for SISO MAP algorithm are discussed and further the idea of composition of Sliding Window and Parallel window is also taken in account using tile graph approach known as Hybrid Tiling. Further to increase the throughput of turbo decoders, pipelining and retiming has been also applied at block level.