Analysis and Design of Cache Memory Cell for Leakage Power Reduction

Abstract

On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into deep-submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventional 6T cell at 180nm technology has been evaluated and is found to be 2.03nW. Also various circuit level leakage reduction techniques such as Autobackgate Controlled Multi-threshold CMOS (ABC-MTCMOS), Gated VDD and Dynamic Voltage Scaling (DVS) has been discussed and applied on conventional 6T cache memory cell. Leakage reduction of 28.5%, 88.7% and 98.3% has been achieved by using ABC-MTCMOS, Gated-VDD and DVS respectively as compared to conventional 6T cell. Further a different architecture for memory cell, that is, 5T SRAM cell has also been adequately designed and analyzed to diminish leakage power consumption. About11.8% reduction in leakage has been achieved by conventional 5T cell than the conventional 6T cell. Using 5Tcell with ABC-MTCMOS, Gated-VDD and DVS, further leakage reduction of 3.3%, 26% and 12.1% respectively has been achieved as compared to the particular case with 6T cell.