Implementation of Memetic Algorithm for Estimation of Node Count and Power Using Various Crossover Operators

Abstract

Low power consumption has emerged as a key design parameter for digital VLSI systems. Therefore, accurate methods are required to estimate the switching activity at the internal nodes of the logic circuits to determine average power dissipation. Since, manipulation of Boolean function is an important element of many logic synthesis algorithms including logic optimization and logic verification of sequential and combinational circuits, therefore, it is important to have efficient methods to represent and manipulate such functions. A major problem with binary decision diagram (BDD) based manipulation is the need for application-specific heuristic algorithms to order the input variables before processing. Therefore, finding a good variable order for ordered binary decision diagrams (OBDDs) is an essential part of OBDD-based CAD tools. For the current problem of variable ordering and for determining signal activity, the technique that has been proposed and used in this thesis work is a Modified Memetic Algorithm (MMA) based technique with different crossover operators (namely order crossover, cycle crossover and partially mapped crossover operator ) that finds an optimal input variable order with an aim to reduce node count for a multi-input multi-output (MIMO) Boolean function and also aim to reduced power dissipation by determining the signal activity using BDD-based probabilistic technique.