Design of Self Biased Rail to Rail Input Operational Amplifier

dc.contributor.authorSharma, Sudhir Kumar
dc.contributor.supervisorIliyas, Mohd.
dc.date.accessioned2009-09-17T09:10:12Z
dc.date.available2009-09-17T09:10:12Z
dc.date.issued2009-09-17T09:10:12Z
dc.descriptionM.Tech. (VLSI Design and CAD)en
dc.description.abstractOperational amplifiers use a large number of external bias voltages. These results in numerous drawbacks, namely, an area and power overhead, susceptibility of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. Self-biased operational amplifiers are free from the above mentioned drawbacks and exhibit the same performance as existing folded casode operational amplifiers, except for a small reduction in slew rate. This thesis work is for the development of new trend of operational amplifier. The technology is shrinking down, portability of electronic systems is gaining more important. With the technology shrinking threshold voltage is not shrinking with the same proportion. So it is useful for operational amplifier to work at any common mode level so a rail-to-rail input stage is a better choice for an operational amplifier. A rail-to-rail input common mode range is an important requirement in operational amplifiers for some applications. Conventional techniques to achieve a constant-gm rail-to-rail complementary N-P differential input stage require complex additional circuitry. In addition, the frequency response and common-mode rejection ratio (CMRR) are degraded. The technique used here in this thesis work is generating a voltage source between source terminals of both N and P differential pair, which keeps effective gate source voltage hence gm constant over the whole rail-to-rail common mode level. Finally, a self biased rail-to-rail input operational amplifier is designed using TSMC 0.35 CMOS technology with a supply voltage of 3.3V. As the input common mode varies, variation in DC gain is up to 3.65dB. The power dissipation of the operational amplifier is 268.5 with unity gain bandwidth 9.17MHz and phase margin of 54.94º. Further process corner simulations have been done for process variation of 15% in threshold voltage , oxide thickness and mobility . Variation in gain in this process variation is 84.5588 dB to 86.2154 dB which is very less. And power dissipation variation from 44.549 uW to around 1 mW.en
dc.description.sponsorshipDepartment of Information Technology (Govt. of India) through SMDP-VLSI Project (Phase – II) and Electronics and Communication Engineering Departmenten
dc.format.extent4604936 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10266/976
dc.language.isoenen
dc.subjectSelf Biaseden
dc.subjectRail to Rail Inputen
dc.subjectOperational Amplifieren
dc.titleDesign of Self Biased Rail to Rail Input Operational Amplifieren
dc.typeThesisen

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