Development of Runtime Abstraction Utility Agnostic to the Flow Type and Implementation of Runtime Enhanced Procedures in the Main Flow of Physical Design

Abstract

From the semiconductor chip having two transistors, to billions of transistors in a single chip, Very Large Scale Integration (VLSI) industry is growing continuously while obeying Moore’s Law. While, product quality is the important criterion for a SoC, time-to-market (TTM) also plays a crucial role for the company to stay ahead of the competitors. While the smaller SoCs like smart phone take 6 months to get implemented, the implementation of server SoC is actually a time hogging step; and in general, it can span from one year to two years, which includes a series of RTL design, synthesis and place and route flow to run multiple times until the design converges. As we are concerned about the back-end design process, our area of interest limits to synthesis and place & route process for now. The aim of our thesis work is to pavé a path for faster TTM. The first step towards achieving faster TTM or smaller runtime is to find out the reasons behind longer runtime which should be followed by modifications in the routines/methods used in synthesis, and place & route flow. In our thesis work, a runtime abstraction utility is proposed and implemented to pick out the actual runtime hoggers in the physical design flows. The utility is able to abstract runtime information at different levels irrespective to the flow type into consideration. A graphical user interface (GUI) is also developed for the same utility which provides interactive way of running the utility. As we know that, finding the actual runtime hogger module is the first step towards the path of providing faster TTM, the thesis work also analyzes a test design having a huge runtime; and provides a set of application variables introduced in the runtime hogger module to reduce the runtime for the synthesis and APR flow.