Power and Area Efficient Multiplier Unit Design for Implementation of Adaptive Filter

Abstract

Adaptive filters are used in various digital signal processing (DSP) applications such as noise cancellation, echo cancellation, channel equalization and system identification. Area-delay and power efficient realization of the adaptive filters has great practical importance for resource constrained DSP applications. The least mean square (LMS) algorithm, which is derived from the minimization of the mean squared error between the output of the adaptive filter and some desired signal, has the advantage of low complexity as well as simplicity of implementation and offers low throughput rate and is suitable for signals having smaller sampling frequencies. In this thesis, main concern is to develop efficient implementation techniques of this algorithm to provide fast convergence of the adaptive filter coefficients and in the same time good filtering performance. As DSP systems can be realized using programmable processors or custom designed hardware circuit fabrication using VLSI technology, low-complexity design is necessary for efficient hardware implementation which requires low area-delay product, high speed of operation and low power consumption. In order to develop area-delay efficient computing structures for LMS-based adaptive filters, Distributed arithmetic (DA) approach using Block LMS (BLMS) algorithm has been proposed which resulted in reduction of area and delay as well as increased throughput as both convolution operation ,to compute filter output, and correlation operation ,to compute weight-increment term, is performed by using the same LUT. Further, multipliers for an important part in filtering process where high speed calculations are required and time taken by multiplication operation is the dominant factor in determining the instruction cycle time of a DSP. Moreover, multiplier lies in the critical delay path and determines the performance of processor, speed of multiplication operation is highly important in DSP operations as it is generally the slowest element in the system. Hence, efficient design and implementation of dedicated squaring and cubing unit is proposed which has reported significant reduction in the power and delay while minimizing silicon area at the same time. The proposed design of DA-BLMS algorithm and Dedicated Squaring unit is successfully implemented in XILINX ISE14.5 using Verilog and VHDL language and Power Efficient cubing Unit is verified at device level using Cadence-Virtuoso ADE.