Pre-Silicon Validation of Performance Monitoring Counters

Abstract

Pre-silicon validation/verification is required to find the bug early in the system. They are easy to find and fix also cheaper to resolve the issue. Performance monitoring unit is a hardware unit which is built inside the CPUs of the X86 family and other architecture families like PowerPC and ARM. The PMONs store the counts of hardware related exercises inside the CPU, and can be utilized to analyze different parts of utilizations running on that hardware. The primary utilization of PMONs is software performance analysis. Performance Validation is being done by programming programmable PMCs with architectural events like number of instructions decoded, number of interrupts received, number of cache miss and a lot more. Intel introduced Performance Monitoring in early Pentium processors with a set of two 40-bit Performance Monitoring Counters and with a set of model-specific performance monitoring counter MSRs. These counters permit selection of processor performance parameters to be monitored and measured. The information obtained from these counters can be used for tuning system, compiler performance and application performance. The motivation behind this project is based on the expectation of the customer for higher performance on latest products. Performance validation at core level gives customers to do depth analysis of generation to generation architecture features and performance parameters. Hardware performance counters helps to obtain the micro-architecture level information. After obtaining the information the bottlenecks of the system are identified and removed which helps to improve application performance. The main goal of this project is running regression and checking the failing test and debugging them.