Design of an Adaptive Analog to Digital Converter

Abstract

The increasing demand for versatile and efficient analog-to-digital converters (ADCs) has prompted the need for innovative designs that can address the challenges posed by diverse signal characteristics. By adding adaptive features to improve its performance under various input signal situations, the presented work seeks to address the drawbacks of conventional designs. The design of an ADC architecture that can dynamically modify its parameters to optimize performance under various operating situations is one of the main goals of this study. The proposed ADC's flexibility is made possible by a mix of artificially intelligent algorithms and more flexible architecture, enabling optimized resolution, speed, and power consumption. The thesis begins with a comprehensive review of existing ADC architectures such as SAR, Flash, Pipelined, Sigma Delta, etc., highlighting their strengths and limitations. Subsequently, the design methodology used for the adaptive ADC is presented, detailing the selection of key components, circuit configurations, and the integration of ML-driven algorithms. Extensive simulations have been conducted using advanced circuit design tools to validate the effectiveness of the proposed idea of an adaptive ADC in terms of resolution and sampling rate. The results show the adaptive ADC performs better than its traditional counterparts, particularly in rapidly changing input signal conditions. The adaptive ADC demonstrates improved accuracy, reduced power dissipation, and enhanced speed, making it suitable for various applications, including biomedical sensor networks and IoT devices. This study also highlights the practical use of the proposed ADC while considering manufacturing issues and real-world limits. It has been argued whether the adaptive ADC architecture is feasible and scalable, opening the door for possible incorporation into commercial electronic systems. In conclusion, this thesis presents a significant contribution to the field of ADC design by introducing an innovative and adaptive architecture. The research expands the theoretical understanding of ADCs and offers practical solutions to address the challenges posed by diverse signal characteristics. The findings of this thesis are expected to have a lasting impact on the design and development of future-generation ADCs, enhancing their versatility and efficiency in various electronic applications. An Analog-to-Digital Converter plays an essential role in the system design, facilitating seamless integration of the digital processing components.Its accuracy and resolution directly impact the quality of data acquisition, enabling precise measurement and control in various applications such as wireless, biomedical, IoT, and sensor networks. ADCs are crucial in capturing real-world phenomena, such as sensor readings or audio signals, and converting them into a format compatible with computers in digital signal processing. Selecting the ADC type and specs is an essential aspect of design that affects the system's overall performance and dependability. Essentially, ADCs link the digital and analog realms, allowing many technologies to merge into modern electronic systems. This thesis presents research on an adaptive analog-to-digital converter with the feature of variable resolution and adaptive sampling. To design an adaptive ADC with varying resolution, an 8-bit SAR ADC is first designed using 180 nm CMOS technology, and then a digitally implemented variable resolution logic is developed. After the variable resolution logic block is implemented, there is less variance in the sample rate, which ranges from 250 MHz to 175 MHz for 8 to 12-bit resolution. According to the simulation results, this ADC achieves an SNDR of 47.4 dB for 8-bit resolution and rises to 72.11 dB for 12-bit resolution. For 8-bit SAR ADC, the FoM of 253 fJ/conversion step is obtained, whereas for resolutions ranging from 9-bit to 12 bits, FoM varies from 168.3 to 35.7 fJ/conversion step. The proposed ADC has an area of 315.86 × 151.30 μm2 .

Furthermore, a time-based sampling technique is used to vary the input signal sampling rate to introduce adaptive sampling in an ADC. This technique allows for effective data representation and lowers the need for data rate to make this design more power-efficient. Using 180nm CMOS technology, the proposed ADC achieves ENOB of 5.21 bits, SNDR of 31.76 dB, and SFDR of 44.31 dB. The proposed ADC sample rate ranges from 64 Hz to 512 Hz, making it appropriate for portable ECG monitoring applications. The FoM of the proposed adaptive sampling ADC is 1.02e-07 j/conversion-step for 64 Hz and 1.48 e-05 j/conversion-step for 512 Hz. Also, an algorithm is developed to enhance the linearity range of a digitally controlled Oscillator. The measurement results show that without a machine learning algorithm, the control voltage of a VCO (Voltage Controlled Oscillator) linearity range is 0.28 V to 0.40 V, increasing to the range from 0.1 to 1.8 V after applying the proposed machine learning algorithm. The maximum gain variation of 3.71% is observed at FF with respect to the TT corner after using the proposed machine learning algorithm. Phase noise is -115.3 dBc/Hz with the algorithm and -105.1 dBc/Hz without it. The improved linearity range in the VCO transfer curve results in a 10.2 dB improvement of phase noise that improves the overall quality of the ADC architecture. Once linearity is enhanced in the VCO, this algorithm is also implemented in an ADC to minimize

its errors further. After implementing this algorithm in a 4-bit Flash ADC, the differential non- linearity (DNL) is improved from ±0.63 LSB without algorithm to ±0.45 LSB with the

algorithm. Also, the INL and SNDR have been improved using this algorithm. This research highlights the need for adaptation in improving analog-to-digital conversion by offering a versatile solution to dynamic signal processing problems. The proposed approach demonstrates encouraging developments.