Implementation of Sequential Decimal Multiplier

Abstract

Multiplication is the most important operation among all the four arithmetic operations during the last decade in various fields which is in the top list of research. Decimal multiplication is gaining very high popularity in recent years in the fields like analysis of finance, banking, income tax department, insurance and many more such fields. The hardware implementation of this has become a very important and interesting topic of research. There are a number of multipliers such as serial multiplier, parallel decimal multiplier, booth multiplier, Wallace tree multiplier, combinational decimal multiplier, sequential decimal multiplier, array multiplier and sequential multiplier. Each multiplier has its own advantages and disadvantages. Among all these multipliers, the implementation of parallel decimal multiplier is considered to be the hardest because of its high cost of area. The processor industries have implemented a new version of multipliers which is sequential decimal multipliers so as to reduce this high implementation cost. The problem with this sequential decimal multiplier is its high latency. In the reported work, the focus is to generate a sequential decimal multiplier with lowest possible area, delay and power consumption. The BCD-8421 coding mechanism is used to generate easy multiples and partial products.