Test Data Compression Using Adaptive Block Merging with Eight Coding Run-Length Technique

Abstract

With the increase in the complexity, the amount of test data on chip is increasing rapidly. This increases the possibility of manufacturing imperfections at deep sub-micron level. Due to increase in test data volume, the amount of memory required to store huge test set data is increased. This puts constraints on ATE memory to store test data. One of the approaches to address this issue is the use of BIST, but for this, (intellectual property) IP core should be BIST ready. This rise in test data volume leads to an increase in test application time. So, there is a requirement to reduce the test data. If the test data is compacted then the ATE memory required to store the test patterns decreases. This will reduce the requirement of external hardware of memory to support ATE.

Thesis report consists of the study of several test data compression schemes. Various Code based techniques have been studied, such as, Run-length based (Golomb code, FDR, EFDR and AFDR), Statistical code based (Selective Huffman and Optimal Huffman) and Dictionary based (Bitmask and dictionary selection) compression schemes. A new Modified BM-8C test compaction scheme has been proposed based on the block merging and eight coded technique. ABMEC is compared with the existing techniques based on the compression ratio and test application time. When applied to the various benchmark circuits, ABM8C technique improves the compression ratio and reduces the test application time. This decreases the memory requirement of ATE to store the test patterns. It also reduces the dependency of cores to the BIST ready.