DFT and Front End Methodology in D2D Analog Mixed Signal IPs

Abstract

The main objective of this thesis is to improve the fault coverage of a digital design by targeting specific fault types such as pin constraints, black box faults, and tied cells. The study primarily focuses on two widely used fault models: Stuck-At Fault and At-Speed Fault. A key part of the approach involves addressing black box faults by ensuring that the inputs and outputs of such blocks become observable during the test phase. This improves visibility into areas of the circuit that are otherwise difficult to access, allowing for more thorough testing. The methodology begins with a gate-level netlist, which undergoes scan insertion to enable better control and observation of internal nodes during testing. The result is a scan-enabled version of the netlist. Throughout this process, various Design Rule Checks (DRCs) are performed to identify rule violations or structural issues that could affect testability. Faults detected at this stage are analyzed and corrected to prevent them from impacting the final coverage results. Once the design has been cleaned of rule violations and structurally improved, pattern generation is executed on the updated netlist. These test patterns are designed to activate and propagate faults to observable points, increasing the likelihood of detecting them during test application. The overall process leads to a significant enhancement in fault coverage, ensuring that more potential defects are identified during manufacturing tests. Ultimately, this improves the design’s testability and contributes to the production of more reliable and higher-quality semiconductor devices. Keywords: DRC, Scan, Black Box, Stuck At, At-Speed