Implementation of LMS Calibration Algorithm for 12-bit Pipelined ADC

Abstract

Pipelined ADCs are the most powerful, most efficient among all and widely used ADC because it offers an attractive combination of high speed, high accuracy and low power consumption. But there are some errors in the pipelined ADC which limits its accuracy and speed. These errors are finite gain error, capacitor mismatch, offset errors and amplifier non-linearity. As the technology advances to deep sub-micron technology, high speed, lesser area and lower power consumption are the major concerns. This performance levels can easily be met in scaling dimensions of MOSFET for digital circuits. But, in analog circuits it is difficult to achieve all upto a remarkable level without degrading the performance. It happens due to certain errors in them as mentioned above. So, in order to meet the requirements of low power, low area and high speed in analog circuits as well, digital calibration algorithms are used based on digital signal processing techniques. The present work is the implementation of one such calibration algorithm using LMS technique to calibrate 12-bit pipelined ADC with 1.5 bit/stage architecture. First of all the various errors are studied and an equation is derived considering the effect of all the errors. Then that equation is modelled in verilog in binary. This requires a use of floating point multipliers and adders which are implemented using booth’s radix-8 algorithm in order to reduce area and delay. For reducing the delay in adding the partial products generated by Booth’s algorithm, various compression techniques are introduced like the use of carry save adders. Then the design is synthesized and verified on FPGA in order to generate the calibration hardware.