Mapping of Application-Specific NOC Using DPSO Technique

Abstract

Advances in semiconductor process and design technology enable the design of complex System On Chips. Traditional IC design in which every circuit is designed from scratch is more and more being replaced by a design style based on embedding large reusable cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing, test, design, validation and debug. The manufacturing process may result in defected chips, for instance due to the base material defects, and therefore testing chips after production is important in order to ensure fault-free chips. The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. To reduce test cost, SoCs are being increasingly tested in modular fashion, i.e. their various cores modules are tested on the bases of divide and conquer techniques. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. Network-on-Chip (NoC) architecture with regular topology provide scalable platform for designing System on Chip (SoC) with large number of cores. Designer come across a number of challenges and opportunities while developing products and applications using the NoC architecture. One of the challenge is mapping of IP cores onto NoC architecture such that communication cost is reduced. Discrete Particle Swarm Optimization (DPSO) mapping scheme is used to generate optimize mapping configurations for NoC architecture with respect to communication cost. Total cost function is evaluated for these generated mapped configurations considering the factors Communication Cost, Robustness Index and Contention Factor. Communication cost is used to compare different mapping solutions with respect to power consumption and performance. Robustness index gives the idea of fault tolerance properties of NoC. Contention factor gives information about latency, throughput and communication energy consumption. The simulation results are calculated for application specific bench marks circuits VOPD, MPEG-4, PIP and DVOPD.