FPGA implementation of radix-10 parallel decimal multiplier

Abstract

Multipliers are being increasingly used in DSP processors, filters, communications systems etc. With the rising complications of technology, high-speed systems are in great demand. On comparison with other operation in an arithmetic logic unit the multiplier consumes more time and power. Hence the demand to design or implement multipliers with optimal speed, power and area has increased. This dissertation includes the implementation of decimal multipliers which are arranged in parallel, with the idea of reducing delay. The partial products are generated in parallel by using signed digit radix-10 recoding of the multiplier and a simplified box of multiplicand multiples. Number of partial products are reduced by creating a tree structure of partial products. The same is developed by using a new algorithm known as decimal multi-operand carry save addition. This uses unconventional decimal coded number systems, which largely improves the area and latency of the prior or existing design. It includes optimized digit recorders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters (a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated). The generation of partial products are developed parallel by using signed-digit (SD) radix-10 recordings of the multiplier and a simplified set of multiplicand multiples. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix-8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication. The modules have been designed in Verilog HDL, simulated and synthesized using Xilinx 14.5.