Efficient Test Solutions for System on Chip

Abstract

To cope up with the ever growing demands of the market, more and more number of components are being integrated on a single chip. Realization of complete system comprising of heterogeneous mix of digital and analog logic blocks on a common platform has become feasible owing to the advancements in the design and fabrication techniques. Embedded core based integrated design style has proven to be an effective solution for curtailing the production time and needed design effort for creation of such systems. It involves integration of pre- designed and pre- verified IP cores on a single silicon platform to constitute a system on chip or the so called SoC. Such IP cores can be provided either by the same or some third party design houses in hard, soft or firm information formats. Advancements in the semiconductor manufacturing technology have led to the development of 3D structures wherein multiple dies are stacked together in vertical dimension. Such structures offer advantages of much higher complexity, lower footprint, lower average power and increased performance. The interconnections between the various dies are provided using low capacity, high density conducting nails called through silicon vias (TSV). Based on the circuit partitioning, 3D SoCs can be categorized as fine grain partitioned SoCs or coarse grain partitioned SoCs. In fine grain partitioned SoC design style, the various core elements may be distributed over multiple dies while in coarse grain, the cores are still 2D but the entire system can be spread over different dies. The necessary interconnections for functional access, power distribution etc. is made possible by using the through silicon vias. Another technological advancement that has taken place in semiconductor industry is the introduction of on chip network as an alternative for bus based interconnects. Being free from different parasitic effects, it offers the advantages of high performance, efficient utilization of bandwidth, low latency, increased throughput, low power dissipation etc. However, such high end design and manufacturing technologies have brought in new design and test challenges. Manufacturing of billions of components at deep sub-micron level is prone to numerous defects associated with imperfect resolution, misalignment, occurrence of shorts, bridging etc. Such defects can lead to faults which may further degrade the functionality and performance of the systems. To test all the components, they need to be accessed using various input pins and fed with appropriate test patterns. The quality of the systems can be decided by comparing the pre-saved desired outputs with the response of the system to the test patterns which are specifically designed to test the various faults. Increasing level of integration has led to multifold increase in the amount of possible defects which further increases the test data volume. Generation or storage of such a huge test data increases the test cost. Meanwhile, it also increases the time needed to transport the test data between its source and the SoC periphery. Increase in the difference between the on chip components and SoC pins has led to the controllability and observability issues for individual test points.Likewise, other challenges faced by test engineers include: increasing test power, limited test bandwidth, heterogeneous mix of logic styles, increasing on-chip frequency etc. which are making the entire test process a tedious task. To efficiently address the problem of testability of such systems, modular test approach has proven to be a promising solution. It comprises of test infrastructure consisting of test wrappers and test access mechanism which help in providing the necessary isolation and application of test data to the circuit under test. The test solution so developed needs to be optimized to save the test cost. Test time being an integral component of the overall test cost can be reduced by concurrently testing multiple cores. Meanwhile, it is important that the test schedule should not violate the various constraints imposed by test power, test bandwidth, precedence, hierarchical status of the cores etc. The problem of test architecture development for 2D SoCs need to be adapted for 3D SoCs to address the constraint set by maximum number of TSVs available for test purpose. The main objective of the proposed research work has been to develop an efficient test solution for the system on chip. The key contributions include the development of new test data volume minimization techniques and efficient test architecture for 3D SoCs. This thesis describes five test data compression scheme namely, 10 Coded run length based encoding, Selective Count Compatible Run length encoding, Hierarchical Block Merging based Run length encoding, Optimal Selective Count Compatible Run Length Encoding and Adaptive Block Merging Based Run Length Encoding. All the techniques attempt to improvise over the previously proposed test data compression techniques so as to increase the achievable compression efficiency and reduce the test application time. The minimization of test data is done by employing encoding schemes that merges the test data at block and intra block levels. Existence of compatibility and other properties among the test data blocks are utilized to develop the suitable codewords which can replace the long sequence of test bits. Such schemes reduce the needed ATE memory and test application time. A test wrapper optimization technique for fine grain partitioned 3DSoC is presented that reduces the test time by appropriately balancing the wrapper chains. Insertion of the various functional elements is done such that the cumulative TSV requirement of all the wrapper chains does not exceed the maximum TSV limit. An efficient test solution for coarse grain partitioned 3D SoC is also presented that reduces the test cost by successively optimizing the test architecture at die levels. To show the effectiveness, the proposed techniques have been applied to different ISCAS’89 and ITC’02 benchmark circuits. The results so obtained are compared with other previously proposed techniques. Various metrics used to gauge the competence of the test compression techniques include the test compression efficiency, decoder area, test application time and test power. Similarly, the test lengths of the complete SoCs are used to show the effectiveness of the test architectures.