Design methodology for ultra low power Embedded memory IP core

Abstract

This thesis implements and explains the complete design flow of Ultra Low Power Embedded Memory core. It starts from extraction of various subcircuit cells and checking for the design margins as applied to the entire memory circuit on 65nm rule deck. The simulation tool used for the same is HSIM for making faster simulations. Also, entire bitcell analysis flow is carried out to predict the various characteristics of complete SRAM and ROM cell for PVT corners and axis parameters. The automated characterization tool AutoChar is used to carryout the entire characterization procedure and applied procedures are used to predict entire timing violations and power dissipation as well as leakage current measurements. All violations were dealt with so as to obtain the complete datasheet as per customer requirement.