Optimum Physical Design Implementation of Block Level Networking Asic and Its Power Estimation

Abstract

In this thesis research work, an optimum physical design implementation technique for the block level networking application-specific-integrated-circuit (ASIC) has been presented, which significantly reduces the time for a chip to arrive in the market, and it alleviates the noise impact on critical nets. It also presents the power aware physical design flow, which helps in the reduction of the dynamic as well as leakage power. With evolving technology nodes, the leakage power is less controllable from the designer’s implementation point of view. However, the abstract level in digital design is decided mainly by the standard cell. Therefore, an approach is proposed in this research work to reduce the power consumption of the digital block. In this approach, the cell swapping/replacing technique has been utilized, which replaces the ultra-low threshold cells with the low threshold cells. Since, the power dissipation is inversely proportional to the threshold voltage level; therefore this technique is proved to be successful in the reduction of power dissipation. In the current era, the physical implementation for any system-on-chip (SOC) is a time-consuming step; and in general, it would span from one year to two years. The main aim of the physical implementation is to optimize chip in terms of the speed, area, power, and cost. The prime concerns of any company are to reduce the time to market, the operation of chip at the desired frequency and to increase the durability of the product by reducing the power loss. Meeting the operational frequency requirement (corresponding to processing timing) is one of the major design concerns. Therefore, an algorithm has been proposed in this work indicating an optimum flow to fix the different violations observed during the physical design implementation. To conclude, the main objective of the presented research work is to convert the register-transfer-logic (RTL) level netlist to the graphic-data-system (GDS II), which should be clean in design-rule-constraints (DRC), power efficient, timing clean, electron-migration (EM) clean. Therefore, the focus is on a design flow, which should be robust to tackle the last minute changes in the design, and it must be power aware along with the timing sign-off. The simulation results are presented to illustrate the efficacy and efficiency of the proposed algorithm for optimum physical design implementation of the block level networking ASIC and its power estimation.