Design and Verification of IDI VIP for Cache Coherency Management

Abstract

This report focuses on the design and verification of a Verification IP (VIP) for the Interconnect Direct Interface (IDI) protocol, specifically aimed at managing cache coherence in multi-core systems. Cache coherence is a critical aspect of modern computer architectures, ensuring that multiple processors maintain a consistent view of memory. The IDI protocol plays a vital role in facilitating efficient communication and data consistency across different cache levels. The primary objective of this research is to develop a robust and comprehensive VIP that accurately models the IDI protocol's behaviour and verifies its cache coherence mechanisms. The methodology involves the creation of a Bus Functional Model (BFM) that simulates IDI protocol transactions and interactions. This BFM is then integrated into a Universal Verification Methodology (UVM) environment to perform extensive verification and validation. Key findings from this research demonstrate that the developed VIP effectively identifies and resolves cache coherence issues, providing a reliable tool for hardware designers to validate their implementations. The VIP's ability to simulate various cache coherence scenarios and detect protocol violations significantly enhances the verification process's efficiency and accuracy. In conclusion, this thesis presents a detailed account of the design and verification process for an IDI protocol VIP, emphasizing its importance in ensuring cache coherence in multi-core systems. The developed VIP serves as a valuable resource for future research and development in hardware verification, contributing to the overall reliability and performance of advanced computing systems.