Design and Implementation of a High Speed Pipelined Floating Point Multiplier

Abstract

A fast and energy-efficient multiplier is always needed in electronics systems i.e. DSP processors, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI implementation level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, speed and area are always traded off. For DSP processors area and speed are of major concern. But sometimes, increasing the speed also increases the power consumption, so there is an upper bound of speed for a given power budget. For portable multimedia devices, low power and fast designs of multipliers are more important than area.

Since multiplication dominates the execution time of most DSP algorithms, so there is need for high speed multiplier. In this thesis, an architecture for a fast floating point multiplier compliant with the single precision IEEE 754 standard has been proposed. Verilog is used to implement a technology-independent pipelined design. The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. Because floating-point numbers are stored in sign-magnitude form, the multiplier needs only to deal with unsigned integer numbers and normalization. Integer multiplier using Modified Booth’s algorithm and carry save adder is one way to increase the speed of multiplier. Modified Booth’s algorithm reduces the number of partial products to be generated and is known as the fastest multiplication algorithm. Many researches on the multiplier architectures including array, parallel and pipelined multipliers have been pursued which shows that pipelining is the most widely used technique to reduce the propagation delays of digital circuits.

The design is simulated on Modelsim SE and synthesized on Xilinx ISE. The Thesis pays a significant attention to the analysis of multiplier in terms of pipelining and area so as to maximize throughput. After the significand multiplication exceptions like invalid number, infinity, overflow, underflow have also been considered in this multiplier.