Development of Enhanced Test Data Compression Scheme for System on Chip

Abstract

System on chips have turned out to be one of the viable solutions for keeping in pace with the increasing demand of adding more features in a single product. As the whole product lie on the functionality of the SOCs, thus they are required to be tested to make them fault free. But as the complexity of the core is increasing the amount of test data is also increasing. However, the ATEs available at present have not developed to that extent. So, huge test data of complex chips demands more and more ATE memory for storage. This requirement of excess memory adds to cost of ATE as ATEs have to be supported by external hardware. One solution to this is use of BIST, but for this, the IP cores should be BIST ready. So another promising solution is to reduce the test data. If the data is compressed then the pressure on ATE for more memory will be reduced. This work presents analysis and the study of various test data compression techniques. These techniques include run length based codes, statistical codes and dictionary based codes. In the category of statistical codes, codes like selective Huffman and optimal Huffman have been analysed theoretically. Run length based techniques like Golomb coding, frequency directed run length code, extended FDR, alternate run length code, alternate variable code etc. have been compared experimentally. Along with the comparison of run length based codes this thesis report also proposes an efficient and enhanced compression code to improve the efficiency further. This is a multistage code with AVR and Golomb at stage one and 9C at stage two. The efficiency of this has been compared with the already discussed run length codes and it was concluded that it was more efficient than any of these. Also the weighted transition a technique to calculate the average power dissipation has been used. These techniques reduce the test data volume, which in turn reduce memory requirement of the ATE. These also help to reduce the dependency of the cores to be BIST ready