Generic Encryptor/Decryptor Core Implementation of Tiny AES

Abstract

This thesis work presents Designing and Verification of Generic, Single Encryptor/ Decryptor core Unit for area efficient hardware implementation of Tiny advanced encryption standard (AES) algorithm, which can not only implement all the three AES (AES128, AES196, and AES256) algorithms, but also do both the encryption and decryption processes in just single design unit. The AES can be implemented in either software or hardware. Hardware acceleration is the use of hardware to perform a task more efficiently than is possible in software. heavily loaded communication networks, utilization of hardware accelerators for cryptography algorithms is more efficient. The design has been implemented on both Xilinx ISE tool for FPGA flow and Synopsis (Design Compiler) tool for ASIC flow and compared the results for various architectures of design for both the FPGA and ASIC flow in terms of Area, Timing and Power report. A unique feature of this design is that the round keys, which are consumed during different iterations of encryption, are generated in parallel with the encryption process, which can further increase the speed of design.