Design and Implementation of Viterbi Decoder using FPGAs

dc.contributor.authorSharma, Ajay
dc.contributor.supervisorVohra, Harpreet
dc.date.accessioned2008-10-03T10:17:12Z
dc.date.available2008-10-03T10:17:12Z
dc.date.issued2008-10-03T10:17:12Z
dc.descriptionM.Tech. (VLSI Design and CAD)en
dc.description.abstractConvolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. The two decoding algorithms used for decoding the convolutional codes are Viterbi algorithm and Sequential algorithm. Sequential decoding has advantage that it can perform very well with long constraint length. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, is the most extensively employed decoding algorithm for convolutional codes. . The availability of wireless technology has revolutionized the way communication is done in our world today. With this increased availability comes increased dependence on the underlying systems to transmit information both quickly and accurately. Because the communications channels in wireless systems can be much more hostile than in “wired” systems, voice and data must use forward error correction coding to reduce the probability of channel effects corrupting the information being transmitted. A new type of coding, called Viterbi coding, can achieve a level of performance that comes closer to theoretical bounds than more conventional coding systems. The Viterbi Algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing.It is used to detect signals in communications channels with memory, and to decode sequential error control codes that are used to enhance the performance of digital communication systems. Though various platforms can be used for realizing Viterbi Decoder including Field Programmable Gate Arrays (FPGAs) , Complex Programmable Logic Devices (CPLDs) or Digital Signal Processing (DSP) chips but in this project benefits of using an FPGA to Implement Viterbi Decoding Algorithm has been described. FPGAs are a technology that gives the designer flexibility of a programmable solution, the performance of a custom solution and lowering overall cost. The advantages of the FPGA approach to DSP Implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC. The FPGA also adds design flexibility and adaptability with optimal device utilization conserving both board space and system power that is often not the case with DSP chips.en
dc.description.sponsorshipElectronics & Communication Engineering Departmenten
dc.format.extent2481537 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10266/741
dc.language.isoenen
dc.subjectVeterbi Decoderen
dc.subjectFPGAen
dc.titleDesign and Implementation of Viterbi Decoder using FPGAsen
dc.typeThesisen

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