ATPG Simulation and Pattern Generation

Abstract

Because of the technological advancements in the semiconductor industry, we are now able to design ICs with as many as billion transistors while improving the performance and power. However, new challenges arrive with new technologies. The complexity increases with new technologies, and with shrinking size transistors access to internal nodes has reduced and it is now more difficult to diagnose and locate faults. The solution to this problem is designing a testable design so that they function reliably throughout their lifetime. Considering the time and money put in the development of an IC, it becomes very crucial to test it and get a maximum possible yield before handing it over to the customer. This is why around 40% of overall product cost consists of testing of chip. The field responsible for making design testable at an early stage is Design for Testability (DFT). This report explains DFT in detail, techniques involved in carrying out DFT process, like scan insertion, pattern generation and simulating those patterns on netlist.