IDDQ Testing of Two Stage CMOS Operational Amplifier

Abstract

Since the birth of semiconductor industry, current measurement based testing of electronics components has always been an integral part of the testing. It is used to detect gross shorts and is generally referred to as static IDD test. The present form of quiescent current (IDDQ) measurement based testing for CMOS VLSI, known as IDDQ testing used for the detection of bridging faults. IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-supply current. IDDQ stands for quiescent IDD, or Quiescent power-supply current. It is little more than 15-years since the idea of IDDQ testing was first proposed. Many semiconductor companies now consider IDDQ testing as an integral part of the overall testing for all IC’s. In this thesis, a two stage CMOS operational amplifier is designed and Design for Testability method for this two-stage CMOS amplifier, based on IDDQ testing, for improving fault-coverage and testability is discussed. This test method takes the advantage of good fault coverage. Fault detection is achieved using a simple Built in Current Sensor (BICS), which introduces insignificant performance degradation of the Circuit under Test (CUT), to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness, cost effectiveness and capability of Built in Self Testing (BIST) implementation. It can also be generalized other CMOS analog and mixed-signal integrated circuits. The technology used is TSMC 0.35um, 3.3V CMOS N-well process for the designing of CMOS Op-amp. The value of the load capacitance is taken as 3pF.