Ultra Low Power Standard Cells Library Developement In 90nm Technology - OAI, CLKMUX, TLATCH, DFF, SDFF

Abstract

Electronic products have long become an integral part of the modern lifestyle. Demand and supply of such products with smaller size, lower power consumption and better performance are ever increasing. Some of the driving factors include portability, mobility, accuracy and increased performance demands. This in turn impels the manufacturers to incorporate many methods such as decreasing the component sizes, making operations battery powered, choosing improved heat tolerant packaging materials and more. The field of electronics has made quite a leap and come a long way, starting with vacuum tubes, transistors, MOSFETS to the Integrated circuits. Today's electronic circuits carry thousands of systems all on a single chip. This technology migration has been relatively smooth until the sub-micron feature length for CMOS technologies. As we approach the rear end of deep sub micron technologies, the reliability of circuit performance has started facing serious challenges. This thesis reviews the forces that caused the power problem, the solutions that were applied, and what the solutions tell us about the problem. As systems became more power constrained, optimizing the power became more critical, viewing power reduction from an optimization perspective provides valuable insights. Leakage due to scaling down CMOS device sizes will be the major power consumption source in cell based IC design in a few years. This work addresses the problem of this leakage, investigating the possibilities of utilizing alternative logic families instead of static CMOS for the creation of a low leakage cell library. For this purpose, MTCMOS, CPL and Domino logic are investigated for leakage characteristics and are found unusable for low leakage design. Using cell libraries of small logic cells for IC design is found to be the major reason for much of the leakage. In this thesis, a novel logic gate design with low leakage is proposed. Traditionally, the subthreshold leakage through a logic gate depends on the applied input vector. In order to reduce leakage power, we stack an extra transistor in the large leakage path and applying substrate biasing technique. The proposed structure induces low leakage current under all possible inputs. Compared to the conventional CMOS logic circuit design, the simulation results show that the proposed logic circuits not only reduce significant leakage power dissipation, but also keep similar circuit performance as conventional CMOS logic circuits.