Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/714
Title: Design and Implementation of Single Precision Floating Point Multiplier
Authors: Singh, Sarbjeet
Supervisor: Singh, Kulbir
Keywords: Floating Point Arithmetic;Single Precision Floating Point Representation,;Results and Verification;Design and Implementation
Issue Date: 29-Sep-2008
Abstract: Floating Point Arithmetic is extensively used in the field of medical imaging, biometrics, motion capture and audio applications, including broadcast, conferencing, musical instruments and professional audio. Many of these applications need to solve sparse linear systems that use fair amounts of matrix multiplication. The objective of this thesis is to design and implement single precision floating point cores for multiplication. The multiplier conforms to the IEEE 754 standard for single precision. The IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754) is the most widely used standard for floating-point computation, and is followed by many CPU and FPU implementations. The standard defines formats for representing floating-point numbers (including negative zero and denormal numbers) and special values (infinities and NaNs) together with a set of floating-point operations that operate on these values. It also specifies four rounding modes and five exceptions. Rounding modes for this multiplier are round to nearest even, round to zero and round to infinity. Exceptions used in this multiplier are invalid operation, inexact, underflow, overflow, infinity, etc. The design is implemented on ModelSim SE and has been synthesis and simulated on same tool. The thesis pays significant attention to the analysis of the multiplier cores in terms of pipelining and area so as to maximize throughput. In order to perform the floating point multiplication, a simple algorithm is realized. The exponent are added first and then subtracted from 127. The significands are then multiplied and result is determined. The result is then normalized. Any exceptions (like invalid, inexact, zero, infinity, etc) are checked. This multiplier has five stages which are pre normalization, significant multiply, post normalization, except and floating point unit. This multiplier performs 32 bit multiplication of the floating point numbers. Exception and rounding are also considered in this multiplier.
Description: M.Tech.(VLSI Design and CAD)
URI: http://hdl.handle.net/10266/714
Appears in Collections:Masters Theses@ECED

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