Ultra Low Power Standard Cells Library Development in 90 Nm Technology – AOI, TBUFF, SRLATCH, EDFF, MDFF

Abstract

Over the last two decades, low-power design has become a concern in digital VLSI design, especially for portable and high performance systems. As technology scales into the Deep Sub-Micron (DSM) regime, standby subthreshold leakage power increases exponentially with the reduction of the threshold voltage. Therefore, effective leakage minimization techniques are becoming a necessity. Variable Threshold CMOS (VTCMOS) has emerged as an effective circuit-level technique that attains a high performance, while standby subthreshold leakage is minimized by providing substrate biasing. The VTCMOS low-power design methodology involves an iterative design process that involves an area versus power tradeoff and timing versus power tradeoff. As a result, the technique needs to be integrated into the principal design environment. In this thesis, the characterization of different components of standard cell is performed using worst-case and best-case ASIC technology libraries. The worst-case library is characterized by a supply voltage of 1.08V, operating temperature of 125°C, and slow process corner. The best-case library is characterized by a supply voltage of 1.32V, operating temperature of -40°C, and fast process corner. The technology libraries are developed for the IBM 90nm technology. The CMOS nonlinear delay models are used for delay calculations. Variations in operating temperature, supply voltage and manufacturing process causes performance variations in electronic networks. Using different operating conditions, the timing of the design under different environmental conditions can be evaluated. The technology library contains information used for the following synthesis activities: • Translation – functional information for each cell • Optimization – area and timing information for each cell (including timing constraints on sequential cells) • Design rule fixing – design rule constraints on cells