Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/573
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dc.contributor.supervisorAggarwal, RinkleEnglish
dc.contributor.authorManpreet-
dc.date.accessioned2008-08-12T13:03:19Z-
dc.date.available2008-08-12T13:03:19Z-
dc.date.issued2008-08-12T13:03:19Z-
dc.identifier.urihttp://hdl.handle.net/10266/573-
dc.descriptionCSED, M.E.(CSE)en
dc.description.abstractThe basic way to achieve high-performance, high-reliable computing is to use multiple processors linked by one or more shared buses. Such multiple bus systems offer the advantage of low hardware cost, and graceful degradation in the presence of faults. There are many different ways to organize computational structures to exploit parallelism. Many research efforts around the world are being conducted with the purpose of determining the hardware and software organizations that are best suited for general purpose parallel processing. The communication subsystems linking processors, memory modules and input/output controllers in a parallel processing subsystem is one of its most important architectural features and has a profound impact on system capabilities, performance, size and cost. An interconnection network of the processors that provides the desired connectivity and performance at minimum cost is required for communications in parallel processing systems with a large number of components. Multistage interconnection networks play an important role in parallel computing systems. In multistage interconnection the fixed inter stage connections between adjacent stages exist with a number of switches at each stage that are dynamically set to establish the desired connection to route the requests from input to the output. The distribution of switches as well as their complexity is very important in designing multistage interconnection networks. The important issues in the study of multistage interconnection networks are estimation of complexity, fault tolerance, reliability and cost. FT network is a single switch fault-tolerant. If both switches in a loop are simultaneously faulty then clearly some sources are disconnected from some destinations. In this thesis two fault-tolerant irregular MINs FT-1 and FT-2 are proposed. FT-1 Network is a multipath, dynamic MIN which is a modified form of Four Tree (FT) Network. It has been found that FT-1 network is having better permutation capabilities, less cost and high reliability than FT whereas FT-2 have decreased path length, high permutation capability and is more fault-tolerant.en
dc.format.extent596090 bytes-
dc.format.mimetypeapplication/pdf-
dc.language.isoenen
dc.subjectMultistage Interconnection networks, Reliability, Permutation passibility, fault toleranceen
dc.titleOn Fault Tolerant Irregular Multistage Interconnection Networksen
dc.typeThesisen
Appears in Collections:Masters Theses@CSED

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