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http://hdl.handle.net/10266/5688
Title: | Radiation Hardened Flip Flop Design |
Authors: | Arushi |
Supervisor: | Kushwaha, Madhu |
Keywords: | Radiation Hardening;Radiation Strikes;Single event upset;Off Nodes;Flip Flops |
Issue Date: | 22-Aug-2019 |
Abstract: | Device scaling has become an important part of very large scale integration (VLSI) design that can result in faster and denser integration of devices. Increased speed of data transfer, ability to achieve multiple tasks simultaneously and better performance are some of the main advantages of scaling. Subthreshold leakage, dynamic power dissipation and short channel effects are some of the reasons predicted as the disadvantages of transistor scaling. Density of memory elements also keeps on increasing which leads to increased susceptibility of the device nodes toward the radiation. Thus, increasing susceptibility of the device nodes is an add on drawback to scaling of technology node. Earlier, radiation had a prominent effect on integrated ICs in aerospace applications only but due to continuous scaling, it has become a serious hazard at ground level also. In digital electronics, flip flop is the basic sequential circuit which is used to store the state information. Under the influence of radiation, performance of CMOS flip flop circuits get disturbed. Power dissipation, robustness and propagation delay are some of the parameters which are considered while designing a RADHARD flip flop. This thesis work contains the analysis of radiation induced soft errors on 90nm technology node CMOS circuits. It targets to design low power flip flop along with sufficient immunity towards the radiation. Several state-of-the-art designs like DICE, TMR and Single Phase Clocked Design have been implemented. Virtuoso (Cadence) tool has been used to design the structures of flip flops with 1.2V as the supply voltage. An algorithm has been proposed to find out the MOSFETs in cut off region and to remove redundant nodes. It checks the output state of flip flop to observe the effect of radiation strike on it. This algorithm is well implemented on the RADHARD structures along with the proposed design. Analysis has been done on these RADHARD structures on the basis of delay, power and critical charge. |
Description: | MTech (VLSI Design) Dissertation |
URI: | http://hdl.handle.net/10266/5688 |
Appears in Collections: | Masters Theses@ECED |
Files in This Item:
File | Description | Size | Format | |
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ARUSHI(601762004).pdf | 2.22 MB | Adobe PDF | View/Open |
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