Please use this identifier to cite or link to this item:
|Title:||Calibrated High Performance Programmable Low Drop Out Voltage Regulator For PHY Drivers|
|Keywords:||Calibration, settling time;line regulation;Leaker current;compensation;PHY Driver;PSRR|
|Abstract:||A calibrated high performance programmable low drop out (LDO) regulator for PHY drivers, is presented in the thesis. The designed LDO is capable of generating five different regulated voltage levels, starting from 400mV to 600mV, with a level increment of 50mV and has the capability to drive up to 40mA current. These voltages are generated corresponding to five different reference voltages applied at the input of error amplifier. For generating reference voltages, resistive ladder is employed. The normal resistive ladder tapping points give voltages which show variations of about ± 20% with respect to original value. Calibration of LDO helps in reducing this variations to as low as ± 5% . The proposed LDO has been designed and simulated on 10nm CMOS technology process. Compensation technique employed for stability helps in settling the response within 23ns. Compensation technique employed for leaker current makes our LDO to work under two different ranges i.e. from no-load to 2.5mA and from 2.5mA-40mA. Usage of this compensation technique helps in reducing the leaker current up to 1.5 times. During driving PHY drivers with voltage power supply of 0.4V, provided by our LDO, common mode noise of less than 12mV is noted. The working input frequency of driver is 4.5 GHZ. The differential voltage levels varies from -205.6 mV to 206 mV and alternating current in range 1.991 to 2.19 mA flows through the output resistance of driver.|
|Appears in Collections:||Masters Theses@ECED|
Files in This Item:
|601662008_harpreetSingh.pdf||3.08 MB||Adobe PDF|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.