Design of a Low Power 8T SRAM Cell with Improved Stability

Abstract

SRAM is a type of semiconductor memory and typically used for CPU cache and focused on reducing power and to improve the stability of SRAM cells. The total die area of-the modern SOCs is 70% covered byEmbedded_memories. The SRAMs are continued to-be the most important part of microelectronics such as a system on chip application, high performance server processors, multimedia, wireless applications etc. In this thesis work, stacked logic style have been employed to modify the conventional 6T SRAM cell which in turn reduces the static and total power dissipation at the cost of increase in write and read delay of the proposed cell. First of all, a conventional 6T SRAM cell has been simulated and the circuit is modified with using stacked logic style with two more transistors and the simulation results shows a significant reduction in power dissipation and improvement in stability of the cell. The static power of a proposed cellhas been reduced by 46.4 % as compared to conventional 6T SRAM cell and total power has been decreased by 30.2 %. Although the write delay and read delay of the proposed cell has been increased by 29.8 % and 8.9 % in comparison to published 8T SRAM cell, the stability of the proposed cell has been improved significantly. The stability parameters such as write trip current (WTI), static voltage noise margin (SVNM), static current noise margin (SINM) of proposed 8T SRAM cell have been improved by 27.7 %, 53.3 %, 1% respectively as compared to the conventional 6T cell and 71.9 %, 4 %, 42.8 %, respectively as compared to the published 8T SRAM cell.The Write trip voltage (WTV) of the proposed cell has been decreased by 12.6% as compared to conventional 6T cell and 13.4 % as compared to the published 8T SRAM cell, respectively. This shows that the proposed 8T SRAM cell is much more stable than other published 8T SRAM cells. Allthe simulation were have been done in Cadence Virtuoso tool at 90nm technology.