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|Title:||Back End Memory Compiler Validation|
|Keywords:||BackEnd Compiler;Cut Library;Memory Validation;Layout;NetList;Abstract View|
|Abstract:||We use various electronic gadgets in our daily life. Everything from cooking to music uses electronics or electronic components in some way. These electronic gadgets like cell phones, touch sensors, desktops contain silicon chip which is intended to perform a specific task. Inside each silicon chip is a semiconductor intellectual property core, IP core, or IP block which is a reusable unit of logic, cell, or integrated circuit (commonly called a "chip") layout design that is the intellectual property. This intellectual property also called as cut library at initial level is generated using Back End Memory Compiler product. This cut library or intellectual property is generated after cut generation. An Intellectual Property contains various views like CDL (Circuit Design Language), GDS (Graphical Design System), LEF (Library Exchange Format), etc. To ensure correct working of device, Intellectual Property must be correct technically and in terms of functionality. This is possible if its various views are validated. Back End Memory Compiler Validation is an automated tool to validate the various views of a cut library (Intellectual Property at its initial stage). It saves much of time involved in validation of cut library and also validates the BE Compiler product used to generate the cut library. This tool reduces the risk involved in case errors are found at final stage of IP delivery since all errors are detected at initial stage itself. Thus in order to provide client with correct and dynamic memory, Back End Memory Compiler Validation product is assisting the needful.|
|Appears in Collections:||Masters Theses@CSED|
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|801632024_Manpreet_CSED_2018.pdf||1.55 MB||Adobe PDF|
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