Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/4645
Title: Optimization of CLEFIA Algorithm for Information Security in E-Healthcare Devices
Authors: Bharadwaj, Isha
Supervisor: Bansal, Manu
Keywords: Internet of Things;E-Healthcare;Information Security;Lightweight Cryptography;CLEFIA;Optimisation
Issue Date: 11-Aug-2016
Publisher: Thapar University
Abstract: The advancement in technology has led to the emergence one of the best innovation named Internet of Things (IoT). It enables objects with RFID, smart sensors, communication technologies, and Internet protocols to allow them to communicate with each other and take smart decisions. The IoT has a variety of application domains, including E-Healthcare. E- Healthcare aims in providing instant health solutions to patients’ by connecting them directly to the medical professionals. Electronic sensors are used to collect medical data from the patient's body and transmit it to the healthcare system. One of the major concerns regarding smooth application of E-Healthcare is information security. It is essential to ensure trust and data secrecy from the starting throughout the medical treatment to prevent any unauthorized access or unnecessary interruption as this may lead to wrong medical treatment of patients’. Therefore, data encryption is necessary but due to the limitations in device area, computing complexity and power consumption of smart devices, the performance and efficiency of conventional algorithms is not up to mark. In this work study of NIST recommended lightweight encryption algorithm CLEFIA is done. The flow of algorithm is thoroughly studied along with the techniques that can be used to optimize it. The main aim is to optimize the algorithm in terms of area utilisation and efficiency by modelling S-Boxes, Diffusion Matrices and use of Lookup Tables. The work is done at both software and hardware level. The compilation of CLEFIA algorithm is done on GCC compiler and simulation on TSIM simulator. The optimization in terms of cycle count and cycles per instruction at software level is achieved. There is 75% reduction in cycle count and 5.8% improvement in cycles per instructions. At hardware level, optimized synthesized code is generated for xc5vlx50t-3 board of Virtex-5 Family and reduction of 29% in area is seen with increase of 33% in efficiency.
Description: Master of Technology -VLSI
URI: http://hdl.handle.net/10266/4645
Appears in Collections:Masters Theses@ECED

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