Please use this identifier to cite or link to this item: http://hdl.handle.net/10266/4315
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dc.contributor.supervisorAgarwal, Alpana-
dc.contributor.authorSingh, Anil-
dc.date.accessioned2016-09-27T11:19:10Z-
dc.date.available2016-09-27T11:19:10Z-
dc.date.issued2016-09-27-
dc.identifier.urihttp://hdl.handle.net/10266/4315-
dc.descriptionPh. D.en_US
dc.description.abstractPipelined ADC is a popular choice for applications requiring high sampling rates of the range of 50-100 MHz and resolution of up to 12 bits typically which can be extended using different calibration techniques. Resolution is mainly limited by various non-idealities existing in a switched capacitor (SC) implementation of Pipelined ADC stage such as offset, capacitor mismatch, finite amplifier gain, amplifier non-linearity etc. These errors cause linear as well as non-linear errors in the ADC output; the effect of such errors can be mitigated using a calibration technique. So, it is important to understand the various errors, their sources and their impact on total ADC output. Therefore, various pipelined ADC errors occurring in a stage and their impact on overall ADC characteristics are modeled and analyzed using MATLAB. Targeting low power, low area and low cost, an opamp-less fully differential MOSFET-only pipelined ADC stage is presented in TSMC 0.18μm digital CMOS technology with power supply of 1.8 V. It is based on 1.5-bit/stage architecture and uses the charge pump technique to achieve the inter stage gain of 2. Furthermore, stage is independent of capacitor mismatch and avoids the use of power hungry opamps thus reduces the power consumption and Silicon area. In the present research work, MOSCAPs are used in place of MIMCAPs to reduce the manufacturing cost and Silicon area further. Proposed MOSFET-only stage suffers from only gain error. A 10-bit 100 MS/s pipelined ADC is designed using the proposed stage and digital background calibration is performed to compensate the missing codes resulted from the gain error. Before calibration SNDR and SFDR of the pipelined ADC is 39.61 dB and 40.39 dB respectively which increase to 66.78 dB and 79.3 dB after calibration. Also DNL improves to +0.6/-0.4 LSB and INL improves from +9.3/-9.6 LSB to within ± 0.5 LSB. Total power consumption of the ADC is 16.53 mW. A design methodology is proposed to design the MOSFET-only charge pump based pipelined ADC. Following this, a MOSFET-only charge-pump based pipelined ADC can be designed with lesser iterations and design efforts, and reduces the time to market. Designing of various building blocks of the proposed stage along with the tradeoffs are discussed.en_US
dc.description.sponsorshipElectronics and Communication Engineering, Thapar University, Patiala and Department of Electronics and Information Technology (DeitY), Government of Indiaen_US
dc.language.isoenen_US
dc.subjectCharge pumpen_US
dc.subjectMOSFET-onlyen_US
dc.subjectPipelined ADCen_US
dc.subjectdigital CMOS technologyen_US
dc.subjectdigital background calibrationen_US
dc.titleStudies on OPAMP-Less Pipelined Analog to Digital Converter for Deep Submicron Technologiesen_US
dc.typeThesisen_US
Appears in Collections:Doctoral Theses@ECED

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