Please use this identifier to cite or link to this item:
http://hdl.handle.net/10266/3984
Title: | Real Time Implementation of Sobel Edge Detector on FPGA |
Authors: | Singhal, Dhruv |
Supervisor: | Kumar, Vinay |
Keywords: | FPGA, HDL, Sobel, Verilog, VGA |
Issue Date: | 2-Aug-2016 |
Abstract: | Image processing is a computationally intensive operation and typically done in software using CPU processing power. However, even with the advances in computing technology today, software-based image processing requires expensive and powerful CPUs to perform real-time image processing. This is where a low cost FPGA based image processing solution becomes useful. It eliminates the need for powerful CPUs and at the same time can perform real-time processing relatively easily. This work presents the implementation of such an image processing solution in hardware, using a FPGA at its core. The high level goal is to detect edges of an image and the algorithm used for this purpose is Sobel edge detection. Edge detection is the fundamental operation in image analysis. It has to be done for any high end application, such as security cameras. There are various image detection techniques available. These include- Canny, Krisch, Lapla1 and Lapla2. As compared to other techniques Sobel has been chosen for the research work, over the other techniques, because of its simplicity and moderate average risk (AVR) to signal to noise (SNR) ratio. |
URI: | http://hdl.handle.net/10266/3984 |
Appears in Collections: | Masters Theses@ECED |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.