Estimation of Noise in High Performance VLSI Circuits

Abstract

Integrated circuit manufacturing industries are striving for cost effective, compact and handheld products in recent years. Therefore, the integration of digital circuits and analog/RF circuits over a common substrate is a viable solution. The system in which the digital and analog/RF block are sharing a common substrate, experiences an unwanted interaction amongst the various blocks. The switching activities in digital circuits inject noise in the substrate which is propagated through the common substrate to the sensitive analog circuits. This substrate noise coupling can therefore degrade the performance of the entire chip. Therefore, the accurate substrate modeling technique is a prime requirement for the analysis of substrate coupling in complex VLSI circuits. Existing substrate modeling techniques were either based on two dimensional simulations which are not sufficient since the substrate problem is inherently three dimensional, or required extraction of empirical parameters which make the models less predictable. In this thesis, a compact and more accurate substrate macromodel is proposed for the estimation of the substrate noise which encapsulates interactions amongst various types of circuits integrated on a System-on-Chip (SoC). This substrate macromodel is mainly dealing with resistive behavior of the substrate and by using the same resistive behavior of the substrate, the macromodel for the uniformly doped substrate as well as for multilayer substrate is developed to analyze the substrate noise coupling between the source and sensor circuits. These macromodels can further be used in complex VLSI circuits to estimate their performance in the presence of substrate noise coupling. The macromodel for the substrate is generics for all types of substrates, but the circuit macromodel is unique for every circuit. The variation in the performance of MOSFET devices in the presence of substrate coupling is presented to discerning the effect of substrate coupling in the MOSFET operation. The complex VLSI circuits are decomposed in small sections (standard cells) for their truthful analysis of substrate noise coupling and these small sections are further combined to develop the original circuit. To estimate the noise in the standard cell, a gate-level circuit macromodel is developed and is further simplified by combining the effects of parasitics. This simplified gate-level circuit macromodel is combined with the substrate macromodel and is then used in circuit simulator to estimate the substrate noise. The validation of this approach is done by applying it on a chain of five CMOS inverters, which are integrated over a high resistive substrate and the overall system is simulated for substrate noise potential which is varying from – 0.6 mV to + 0.6 mV with a capacitive load of 0.6 nH. The above performed technique is further used for the simulation of substrate current in a CMOS inverter which is integrated over a high resistive substrate. A pulse shaped signal with rise and fall delay of 1 ns is applied at the input of the inverter and substrate current is observed at each high-to-low and low-to-high transitions of the input signal. It is observed that as there is advancement in down scaling technology, the substrate current and hence the substrate potential will be more prominent. Furthermore, a novel methodology is proposed to estimate the spectral response of substrate noise generated from the digital section of SoC which is integrated on the high resistive substrate. In this context two contacts are integrated over the top of the substrate, out of which one is considered as source contact (digital section) while the other as sensor contact (analog/RF section). The system is simulated and it is observed that the transmission coefficient S (2, 1) is varying from -40 dB to -80 dB over the entire frequency range, the substrate noise potential is varying from -1.5 mV to +1.5 mV and power spectral density of substrate noise is also estimated. The design and analysis of the inductively source degenerated low noise amplifier (LNA) is also presented in this research work. The minimum noise figure is obtained using the simulation which is observed to be 1.5dB at the resonance frequency of 1GHz. To demonstrate the substrate coupling phenomenon in a complex VLSI system, two different inverter circuits are considered. Out of these two inverter circuits, one is a saturated load NMOS inverter and is assumed as analog part of the SoC, while the other is CMOS inverter and is considered as digital part of SoC. Both are integrated over a common multi-layered substrate. The substrate network is assumed to be pure resistive network and both the inverter circuits are operating on two different frequencies of 10 MHz (analog) and 25 MHz (digital). The substrate noise coupling between these circuits is analyzed through simulation and it is observed that the noise coupling between the circuits exists only when the distance between circuits is of the order of 10 µm to 15 µm. It is further observed that when the input is applied only at analog inverter then no noise coupling between two types of circuits is present and a peak is observed at 10 MHz. But when the inputs at both the inverter circuits are applied, the noise coupling between the circuits exists and two peaks are observed at 10 MHz and 25 MHz. The statistical behavior of the substrate noise is also studied in this research work. The non-Gaussian cyclostationary substrate noise is modeled using a non-Gaussian mixture density and the probability density function (PDF) of non-Gaussian cyclostationary noise (substrate noise) is estimated by maximizing the log likelihood function and using the priori and post-priori updates. To validate this PDF estimation method, the PDF of substrate noise is again obtained by modeling of non-Gaussian noise using the Gaussian mixture density and a comparison between probability density functions (PDF) is also presented in this study.