Algorithm and Architecture Design of DDS Synthesizers for Improved Performance of PLL

Abstract

High speed wireless data communication is playing major role in fast development of modern communication systems. In dealing with this remarkable development, novel technologies and architectures are required to improve the performance of the system and to reduce the cost of equipment. Considering these constraints, hybrid frequency synthesis architectures and techniques have been used to overcome these constraints. The main objective of this thesis is to provide new and efficient ways to design a phase locked loop (PLL), direct digital synthesis (DDS), and hybrid PLL synthesis techniques. These techniques are generally used in various radio frequency (RF) applications, wireless communication, decoding, modulation, demodulation, etc. In the first proposed technique, the emphasis is on reducing phase noise of PLL for pure signal synthesis. For this a mathematical and modeling approach of the system has been furnished, and then output phase noises in terms of its parameters have been predicted. Based on the performance analysis, a new architecture of PLL for the reduction of phase noise is described and its operation has been verified with advanced design system (ADS) simulation tool. With the help of the proposed architecture, the phase noise has been reduced to 33.33 % at 1 Hz, 7.3 % at 100 Hz and 19 % at 100 kHz. The simulation results demonstrate the better performance as compared to the existing techniques. In digital signal processing, PLL is not capable to store and convert phase into its corresponding amplitude for the further processing. Hence, there is need to use digital technique for the synthesis in the feedback loop. This work has introduced a new direct digital frequency synthesizer (DDFS) technique using piecewise linear approximation. The proposed technique allows successive read access to memory cells per one clock cycle using time sharing. The output values will be temporarily stored and read at a later time. The output of this system is a reconstructed signal that is a good approximation of the desired waveform. As a result, the DDFS technique needs only to store fewer coefficients which reduce the hardware complexity significantly. The proposed DDFS technique has been analyzed using MATLAB. The results obtained show improvement of around 1.43 % in spurious free dynamic range (SFDR) over existing results. The results obtained depict the improved performance in comparison with the existing architectures. This technique solved the clock sharing problem, but still it was not suitable for high frequency synthesis. Therefore, new architecture of the DDFS technique has been proposed using Lagrange interpolation and modified quasi linear methods to reduce the area of look up table (LUP) with high resistor transistor logic (RTL) level synthesis. It is used to generate sine waves of different frequencies with the help of a reference input frequency using digital data. Specifically, it has been shown that Lagrange interpolation technique can be employed to yield better class of parabolic functions that can be used to approximate a pure sine wave. This approximation is further corrected by the use of linear interpolation polynomials that suitably reduces the DDFS Lagrange interpolation complexity and helps to get reasonably better results. The proposed design scheme is implemented on XILINX field programmable gate array (FPGA) and suitable hardware analysis has been carried out. The single architecture of DDS was not suitable for high speed based applications to fulfil the requirement of industries. Therefore, fractional sigma delta modulator (SDM) PLL has been proposed for pure signal synthesis. It has been widely used in wireless communication systems because of the high frequency resolution and the short locking time. Based on the theoretical analysis, the design schemes for optimizing the phase noise performance have been proposed and verified by simulation. Finally, an effective technique has been proposed for noise reduction in fractional PLL by CPPSIM simulator. The output phase noise has been reduced to 6.5 %.

In the aforementioned research work, the PLL, DDS, and fractional PLL have been explored and simulated with the help of various configurations, Lagrange interpolation, piecewise linear approximation, SDM, and time sharing technique using ADS, XILINX, MATLAB, and CPPSIM tools.