Study the Performance Analysis of Multi Walled Carbon Nanotube Based VLSI Interconnects

Abstract

The rapid growth in the VLSI technology is mainly due to the continuous reduction in the feature size of device. With the fast developments in the VLSI technology and design, the clock speeds are increasing and clock frequency is reaching in the Gigahertz range. This high speed transmission of signals in high speed applications is enlisting demands on interconnect performance and stressing the previously negligible effects in interconnects such as ringing, signal delay, reflections, crosstalk, etc. As we move into the deep sub-micron level, the channel length of the device decreases to tens of nanometres with the scaling of technology. At this resolution, the die size and device density of the circuit increases rapidly. This increase makes the requirement of long interconnects in VLSI chips. Long interconnects lead to increase in propagation delay of the signal. The area required for the device (MOSFET) has reduced to such an extent that it is insignificant when compared to the surface area required for interconnect, vias and contact routing. This makes the modern VLSI chips more interconnect limited as they have started to dominate on some of the most relevant factors of the digital integrated circuits such as reliability, speed and energy consumption. Therefore, a precise and deep analysis of the behaviour of interconnect is very essential in designing of the VLSI chip. Accurate modelling of on-chip wiring which includes all the parasitic-induced delays and stray coupling is essential to the circuit designer. The parasitic effects increase as the technology is going in deep sub-micron level because of the increase in die size and interconnect lengths along with increasing speed of the chips. Interconnects are predicted to be responsible for 70-80% of the signal delay in high-speed systems. This delay has to be accounted for during the designing process of the chip, failing to which can lead to logic glitches in digital circuits and distortions in analog circuits, ultimately leading to failure of the circuit. Hence it is extremely important for the designers to include the interconnect sub circuitry during the simulation process as efficiently as possible. In this dissertation work, the impedance parameters of copper and MWCNT interconnects at different interconnect lengths are calculated and their effect on performance of interconnect is analysed and compared. The impedance parameters for MWCNT interconnect at different diameters of MWCNTs are also calculated and their effect on the performance of interconnect is analysed.Performance analysis in terms of propagation delay and power dissipation reveal that MWCNT is a more preferable choice compared to copper atglobal interconnects. Both power and delay of MWCNT increases as the line length increases. Also, the performance of MWCNT at different tube diameters indicate that propagation delay improves as the tube diameter increases. Performance analysis in terms of propagation delay and power dissipation at global lengths, reveal that MWCNT performs better than optical interconnects up to a certain length after which the performance of optical interconnect is better. Piece-wise transient analysis is carried out for interconnect at global length. Analytical model using alpha-power law of CMOS inverter driving a π-RLC interconnect has been used to predict the response of the circuit for a fast ramp input signal. The results show that there is an agreement between the results extracted and SPICE simulation results. The discharging time is same for both cases.