Comparative analysis of different bypassing based multiplier

Abstract

Multipliers are the basic building blocks in Digital Signal Processing (DSP) applications, such as filtering and Fast Fourier Transform (FFT). Most of the power is consumed by these multipliers. These are essential subsystems not only limiting the throughput rate but also affecting the power dissipation and silicon area of digital circuits. The operation of multiplication speed is of great concern not only in DSP systems but also in general processors. Parallel array multipliers are widely used for achieving high execution speed. The Braun’s multiplier, a parallel array multiplier is used to multiply the unsigned numbers. For higher bit multiplication, there is corresponding increase in area, delay and power of the Braun’s multiplier. In this project, various bypassing-based multipliers are implemented, which results in reduction of power, delay and area than that of conventional multipliers. These bypassing techniques also reduce the switching activity. Greater the number of zeros, higher power reduction is achieved. in this project, a comparative study of area, delay and power is done for 4x4 and 8x8 bypassing-based multipliers targeting Spartan-3E(XC3S500E-4FG320) FPGA system using Xilinx 14.5 ISE platform.